.PHONY: all startbuild startsim lint
# rules for NVBoard
include $(NVBOARD_HOME)/scripts/nvboard.mk

# verilator setting
VERILATOR = verilator
VERILATOR_COVERAGE = verilator_coverage
# Generate C++ in executable form
VERILATOR_FLAGS += -cc --exe
# Make waveforms
VERILATOR_FLAGS += --trace --trace-fst
# Warn abount lint issues; may not want this on less solid designs
# VERILATOR_FLAGS += -Wall
# Verilation for hierarchy blocks runs in parallel
VERILATOR_FLAGS += -j 0
VERILATOR_CFLAGS = -MMD -O3 --x-assign fast --x-initial fast --noassert
# start project
TOPNAME ?= top
NXDC_FILES = ./constr/top.nxdc
INC_PATH ?=
BUILD_DIR = ./build
$(shell mkdir -p $(BUILD_DIR))

OBJ_DIR = $(BUILD_DIR)/obj_dir
BIN = $(BUILD_DIR)/$(TOPNAME)
SRC_DIR = .

SRC_AUTO_BIND = $(abspath $(BUILD_DIR)/auto_bind.cpp)

all: $(BIN)
	@echo "Write this Makefile by your self."
sim: startsim
	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
	@echo "Write this Makefile by your self."

$(SRC_AUTO_BIND): $(NXDC_FILES)
	python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $^ $@
VSRCS = $(wildcard $(SRC_DIR)/vsrc/*.v) $(SRC_DIR)/vsrc/top/$(TOPNAME).v
CSRCS = $(realpath $(wildcard $(SRC_DIR)/csrc/*.c $(SRC_DIR)/csrc/*.cc $(SRC_DIR)/csrc/*.cpp))
CSRCS += $(SRC_AUTO_BIND)
# rules for verilator
INCFLAGS = $(addprefix -I, $(INC_PATH))
CFLAGS += $(INCFLAGS)
LDFLAGS += -lSDL2 -lSDL2_image
$(BIN): $(VSRCS) $(CSRCS) $(NVBOARD_ARCHIVE)
	@rm -rf $(OBJ_DIR)
	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_CFLAGS) --top-module top $^\
		$(addprefix -CFLAGS , $(CFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) \
		--Mdir $(OBJ_DIR) -o $(abspath $(BIN))
# Compile as soon as a hierachy block is Verilated
startsim: VERILATOR_FLAGS += --build
startsim: $(BIN)
	$^

lint: VERILATOR_FLAGS+= --lint-only
lint: $(BIN)

include ../Makefile
